Power Verification Engineer

Power Verification Engineer

    Job Number: 25554575
    Santa Clara Valley, California, United States
    Posted: 21-Dec-2012
    Weekly Hours: 40.00

Job Summary

Imagine what you could do here. At Apple, great ideas have a way of becoming great products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. The SoC hardware development team is looking for a design verification engineer interested in the analysis of power on our mobile product lines. This person would be a member of the SoC power team working with a broad team on developing power patterns for specific use cases such as video playback and video capture.
Key Qualifications

    A strong candidate would have 3+ years of experience in design verification and an interest in power optimization.
    •Familiarity with Verilog and System Verilog.
    •Familiarity with script writing in Perl or Tcl.
    •Familiarity with C, Assembly programming, and associated tool chains.
    •Familiarity with verification environments, RTL design characteristics, simulation tools, and emulation tools.
    •Knowledge of SOC power characteristics and intended usage for mobile products a plus
    •Ability to quickly understand and work with new tools.
    •Good communication skills to work across multiple disciplines.

Description

The engineer would be responsible for creating power patterns of interesting use-cases for power analysis. This includes: •Working with architects to determine the interesting use-cases to simulate (i.e. audio playback, video playback, …) •Creating test cases within the design verification team’s environment. •Creating FSDBs by simulating patterns on RTL and gate-level netlists on simulators or emulators. •Working with logic teams to determine the correct functionality or enhance functionality for power reduction. •Tracking pattern progress through all of the steps above.